1. Field of the Invention
The present invention relates to a switched capacitor circuit, and more particularly, to a switched capacitor circuit used in a voltage controlled oscillator (VCO) that can minimize the clock feedthrough effect thereby preventing a VCO frequency drift phenomenon during calibration and the synthesizer phase locking period.
2. Description of the Prior Art
A voltage controlled oscillator (VCO) is commonly used for frequency synthesis in wireless communication circuits. As Welland, et al. state in U.S. Pat. No. 6,226,506, wireless communication systems typically require frequency synthesis in both the receive path circuitry and the transmit path circuitry.
FIG. 1 shows a VCO circuit according to the prior art. An LC type VCO 10 used in a frequency synthesizer contains aresonator, and the basic resonant structure includes an inductor 12 connected between a first oscillator node OSC_P and a second oscillator node OSC_N. Connected in parallel with the inductor 12 is a continuously variable capacitor 14 and a plurality of discretely variable capacitors 16. The continuously variable capacitor 14 is used for fine-tuning a desired capacitance while the plurality of discretely variable capacitors 16 is used for coarse tuning. The resistive loss of the parallel combination of inductor and capacitors is compensated by a negative resistance generator 18 to sustain the oscillation.
Each discretely variable capacitor in the plurality of discretely variable capacitors 16 is made up of a switched capacitor circuit 20 and each switched capacitor circuit is controlled by an independent control signal (SW_1 to SW_N). Based on the control signal SW_N the switched capacitor circuit 20 can selectively connect or disconnect a capacitor 24 to the resonator of the VCO 10. Different on/off combinations of switched capacitor arrays results in a wider capacitance range of the LC type resonator and hence a wider VCO 10 oscillation frequency coverage.
FIG. 2 shows a switched capacitor circuit 20a according to the prior art. A capacitor 30 is connected between the first oscillator node OSC_P and a node A. A switch element 32 selectively connects node A to ground, and the switch element 32 is controlled by a control signal SW. When the switch element 32 is turned on, the capacitance associated with the capacitor 30 is added to the overallcapacitance in the VCO 10 resonator. When the switch element 32 is turned off, the capacitance looking into the first oscillator node OSC_P is the series combination of the capacitor 30 and the off state capacitance associated with the switch element 32.
FIG. 3 shows a differential type switched capacitor circuit 20b according to the prior art. Differential implementations have much greater common-mode noise rejection and are widely used in high-speed integrated circuit environments. In the differential switched capacitor circuit 20b, a positive side capacitor 40 is connected between the first oscillator node OSC_P and a node A. A positive side switch element 42 selectively connects node A to ground. A negative side capacitor 44 is connected between the second oscillator node OSC_N and a node B. A negative side switch element 46 selectively connects node B to ground. The two switch elements 42, 46 are controlled by the same control signal SW. When the switch elements 42, 46 are turned on, the capacitance associated with the series combination of the positive and negative side capacitors 40, 44 is added to the overall capacitance in the VCO 10. When the switch elements 42, 46 are turned off, the differential input capacitance is the series combination of the positive and negative side capacitors 40, 44 and other switch parasitic capacitance. The overall input capacitance when all switch elements 42, 46 are turned off is lower than that when all switch elements 42, 46 are turned on.
FIG. 4 shows a second differential type switched capacitor circuit 20c according to the prior art. The second differential switched capacitor circuit 20c is comprised of the same components as the first differential switched capacitor circuit 20c and there is also a center switch element 48 used to lower the overall turn-on switch resistance connected betweennode A and node B. All three switch elements 42, 46, 48 are controlled by the same control signal SW. When the switch elements 42, 46, 48 are turned on, the capacitance associated with the series combination of the positive and negative side capacitors 40, 44 is added to the overall capacitance in the VCO 10. When the switch elements 42, 46, 48 are turned off, the differential input capacitance is the series combination of the positive and negative side capacitors 40, 44 and other switch parasitic capacitance. The overall input capacitance when all switch elements 42, 46, 48 are turned off is lower than that when all switch elements 42, 46, 48 are turned on.
Regardless of whether the single ended implementation shown in FIG. 2 or one of the differential implementations shown in FIG. 3 and FIG. 4 is used, when the switched capacitor circuit 20a, 20b, 20c is turned off, a momentary voltage step change occurs at node A (and in the case of the differential implementations also at node B). The momentary voltage step causes an undesired change in the overall capacitance, and ultimately, an undesired change in the VCO 10 frequency. Because NMOS switches are used in the examples shown in FIG. 2, FIG. 3, and FIG. 4, the momentary voltage step change is a voltage drop when the switch elements 32, 42, 46, 48 are turned off.
Using the single ended case shown in FIG. 2 as an example, when the switch element 32 is turned off, charge carriers are injected to the junction capacitance connected between the first terminal and the second terminal of the switch element 32. The injection produces an undesired voltage step change across the capacitive impedance and appears as a voltage drop at node A. This effect is known as clock feedthrough effect and appears as a feedthrough of the control signal SW from the control terminal of the switch element 32 to the first and second terminals of the switch element 32. When the switch element 32 is turned on, node A is connected to ground so the feedthrough of the control signal SW is of no consequence. However, when the switch element 32 is turned off, the feedthrough of the control signal SW causes a voltage step, in the form a voltage drop to appear at node A. Because of the dropped voltage at node A, the diode formed by the N+ diffusion of switch element 32 and the P type substrate in the off state will be slightly forward biased. The voltage level at node A will spike low and then recover to ground potential as the slightly forward biased junction diode formed by the switch element 32 in the off state allows subthreshold and leakage currents to flow. The voltage drop and recovery at node A changes the loaded capacitance of the VCO 10 resonator and causes an undesired momentarily drift in the VCO 10 frequency.
When the differential switched capacitor circuit 20c shown in FIG. 4 switches off, it suffers from the same clock feedthrough effect problem at node A and at node B. The positive side node A has an undesired voltage step change caused by the clock feedthrough effect of both the positive side switch element 42 and the clock feedthrough effect of the center switch element 48. Similarly, the negative side node B has an undesired voltage step change caused by the clock feedthrough effect of both the negative side switch element 46 and the clock feedthrough effect of the center switch element 48. The voltage step change and recovery at node A and node B changes the loaded capacitance of the VCO 10 resonator and causes an undesired momentary drift in the VCO 10 frequency.
It is therefore a primary objective of the present invention to provide a switched capacitor circuit capable of minimizing the clock feedthrough effect, to solve the above-mentioned problem.
According to the present invention, a switched capacitor circuit capable of minimizing clock feedthrough effect is disclosed. The switched capacitor circuit comprises a first positive side switch element for selectively connecting a first positive side node to a third node depending upon a first control signal, wherein the first positive side node is connected to a positive side capacitor. A second positive side switch element is for selectively connecting the first positive side node to a second node depending upon a second control signal, and a third switch element is for selectively connecting the third node to the second node depending upon a third control signal. A sequence controller connected to the switch elements generates the first control signal, the second control signal, and the third control signal.
According to the present invention, a method is disclosed for minimizing clock feedthrough effect when switching off a switched capacitor circuit. The method comprises the following steps: (a) Disconnecting a first positive side node from a third node through a first positive side switch element. (b) Disconnecting the first positive side node from a second node through a second positive switch element. (c) Disconnecting the third node from the second node through a third positive side switch element. Wherein, the first positive side node is connected to a positive side capacitor and the sequence of steps (b) and (c) are interchangeable.
It is an advantage of the present invention that by switching off the switch elements sequentially in an order of decreasing size, the switched capacitor circuit is gradually switched off to minimize the clock feedthrough effect and therefore the undesired drift of the VCO 10 frequency.
It is a further advantage of the present invention that by using a third switch element to isolate the largest switch elements from a ground or power node, the subthreshold and leakage currents passing through the largest switch elements once they are switched off are blocked and the VCO 10 stabilizes to a steady state frequency at a much lower rate.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.